Semiconductor devices are built from a number of different layers deposited sequentially. Hence the lithography techniques and etching process are two vital processes cooperate with deposition used to fabricate the desired pattern and so does a primitive or further device structure.
After the device wafers are processed with a photoresist layer and lithographed to obtain a desired photoresist pattern, the wafers are readied for etching. In an embodiment, the etching process is conducted in a Lam-Alliance series TCP 9400 process system, as shown in the FIG. 1. It includes two load-lock chambers 10, an orientation chamber 18, a transfer module chamber 15 and a number of etching chambers 20. The detailed arrangement of the load-lock chamber 10 is shown in the FIG. 2. In FIG. 2 the wafers had been loaded into a cassette 25 from a process chamber (not shown) before the cassette 25 was transfer to a load-lock chamber 10. The load-lock chamber 10 includes a vacuum pump (not shown) to suck a level of vacuum coming down to about 90 mm torr before the wafers are proceeded to etch. While the vacuum level is about balance to that of the transferred module 15, then a gate 35 of the load-lock chamber 10 is opened. After that, a wafer transfer arm 30 of the transfer module chamber 15 removes a single semiconductor wafer which is within a cassette 25 to an etching chamber 20 for processing i.e. removes the unmasked portions of the wafer via a orientation process in the orientation chamber 18. Generally, the etching techniques consist of dry and wet etching methods. The Lam-Alliance series process system includes several dry etch chambers 20. For performing a dry etching, the environment of the etching chamber 20 is set to maintain to an apt low pressure in accordance with the process requirement. Before the wafer is transferred into the etching chamber 20, the N.sub.2 purge to a vacuum level, which is the same vacuum as the transferred module 15. After the etching process is achieved, the purge process to the same vacuum as the transferred module 15, and then the transfer arm 30 withdraws the etched wafer to the original cassette 25 in the load-lock chamber 10. A second wafer follows sequentially to proceed the etching process. The cassette 25 will not transferred from the load-lock chamber 10 to another process chamber till all wafers are etched away. In an embodiment, each batch of wafers is about twenty-five pieces of wafers.
After etching process is achieved, the gate 35 is closed and N.sub.2 gas is flowed via an N.sub.2 -purge tube 40 into the load-lock chamber 10 to vent the vacuum to the surrounding atmosphere. An another gate 38 of the load-lock chamber 10 is then opened and another transferred arm (not shown) withdraws the cassette 25 to proceed further processes. It is found that some of the corrosive particulate disperse onto the space and walls of the load-lock chamber, and cause the corrosion to occur before a regular cleaning the load-lock chamber 10 commences. The interval between regular cleaning is about processing two thousands piece of wafers, generally. For solving above corrosion and particulate/contamination issue, a conventional approach is by shortening the duty cycle. However, it will pull down the throughput. The invention provides an efficient method to solve above issues.